Features
- Mezzanine board — pairs with an EDT main board (PCI or PCIe), which adds DMA, programmable FPGA resources, and memory
- Port 0: One SFP for 1GbE (optical or electrical) or OC3/12/48 (STM1/4/16) — 1310 nm; all are input and output
- Port 1: One SFP for 1GbE (optical or electrical) or OC3/12 (STM1/4) or OC3/12/48 (STM1/4/16) — 1310 nm; OC48 (STM16) is input only
- FPGAs: Two programmable (one Xilinx Spartan 3 XC3S200 and one Xilinx Virtex II Pro XC2VP4)
- DRAM: Up to 2 GB (DDR) for snapshot recording and data buffering
- Clocks: Two XOs (one per port) for internal reference, each independently programmable from 10 to 215 MHz
The OCMP (formerly OCM) is a mezzanine board that pairs with an EDT PCIe8LX main board to support 1GbE (electrical or optical), SONET OC3/12/48 (SDH STM1/4/16), or both.
The OCMP has two volt-controlled crystal oscillators (VCXOs), either programmable or settable to multiple frequencies. It also has two small form pluggable (SFP) transceivers. Each SFP supports 1GbE (electrical or optical) or OC3/12 (STM1/4), and one also supports OC48 (STM16). The board has up to 2 GB of DRAM for snapshot recording and data buffering.
For details on system requirements and EDT-provided software driver packages, see the specifications for your EDT main board PCIe8 LX.
Datasheet OCMP