Features
- PCIe x8 interface for high-speed DMA and synchronous CML and ECL I/O
- One user-configurable Xilinx Kintex 7 FPGA
- Integrated FIFOs for input and output
- 16 DMA channels, 8 for receive, 8 for transmit
- I/O (standard): 4 CML input/output channels and 4 ECL input/output channels
- CML I/O data rates of up to 1300 Mb/s per channel
- ECL I/O data rates of up to 1400 Mb/s per channel
- Synchronous hardware protocol (each channel has its own independent clock)
- User-accessible VHDL in the FPGA
The PCIe8 CML-ECL is a PCI Express 8-lane interface that enables fast DMA and synchronous I/O to transfer CML and ECL data between an external device and a host computer. 8 bidirectional channels are supported; four CML and four ECL.
The PCIe8 CML-ECL provides one Xilinx Kintex 7 FPGA (XC7K160T) which combines PCIe functionality (for DMA) and UI functionality (for I/O). The buffers are integrated FIFOs for input and output.
Observed data rates on the I/O connector are up to 1300 Mbits per second for the CML channels and up to 1400 Mbits per second on the ECL channels.
The hardware protocol is synchronous: all data and control signals are sampled by a clock transmitted along with them. This sample clock can be generated by the DMA interface, the user device, or both.
EDT provides FPGA configuration files supporting standard operations. Custom configuration files can be requested.
The system must have a PCI Express bus (8, or 16 lanes) that is not dedicated to display use only. See system requirements.
Datasheet PCIe8 CML-ECL